Various nonvolatile memories have been disclosed in the prior art. For example, Mitchellx has proposed EPROMs with a self-aligned planar array cell. In this technique, buried diffusion self-aligned to the floating gate avalanche injection MOS transistors are used for the bit lines. Cross point array technology has been disclosed. The self-aligned source and drain will allow this device to be optimized even further for programming speed. See A. T. Mitchellx, "A New Self-Aligned Planar Cell for Ultra High Density EPROMs", IEDM, Tech. pp. 548-553 (1987).
Flash memory is one of the segments of nonvolatile memory devices. The device includes a floating gate to store charges and an element for electrically placing charge on and removing the charges from the floating gate. One of the applications of flash memory is BIOS for computer. Typically, the high-density nonvolatile memories can be applied as the mass storage of portable handy terminals, solid state camera and PC cards. That is because the nonvolatile memories exhibit many advantages, such as a fast access time, low power dissipation, and robustness. Bergemont proposed another cell array for portable computing and telecommunications application, which can be seen in Bergmont et al., "Low Voltage NVG.TM.: A New High Performance 3 V/5 V Flash Technology for Portable Computing and Telecommunications Applications", IEEE Trans. Electron Devices, vol. ED-43, p. 1510, 1996. This cell structure is introduced for low voltage NOR Virtual Ground (NVG) flash memory having fast access time. In the flash array schematic, field oxides (FOX) are formed between cells such that a poly extension on FOX of each cell provides adequate gate coupling ratio. Bergmont also mentioned that the portable telecommunications and computing have become a major driving force in the field of integrated circuits. In the article, the access time is one of the key concerns for low voltage read operation. The NVG array uses select devices to achieve a fast access time by reducing the pre-charge time to that of a single segment rather than the full bit-line.
The trend of formation of nonvolatile memories is moving to low supply power and fast access because these requirements are necessary for the application of the mobile computing system. One important key parameter of the high performance memory is capacitive-coupling ratio. The prior art proposed a structure to increase the capacitive-coupling ratio by using hemispherical grained (HSG) silicon to increase the surface area of floating gate. Buried n.sup.+ diffusion layers are formed with self-aligned arsenic ion implantation and the cell structure works at 3V. (Please see Shirai, et al., "A 0.54.mu.m.sup.2 Self-Aligned, HSG Floating Gate Cell for 256Mbit Flash Memories", IEDM Tech. Dig., p.653 (1995).)
Flash memory needs charges to be held in the floating gate for long periods of time. Therefore, the dielectric that is used for insulating the floating gate needs to be high performance. At present, the low voltage flash memory is applied with a voltage of about 3 V or 5 V during charging or discharging the floating gate. As is known in the art, tunneling is a basic technology in charging or discharging. In order to attain high tunneling efficiency, the thickness of the dielectric between the floating gate and the substrate have to be scaled down due to the supply voltage is reduced. However, it will degrade the reliability of the dielectric when the thickness of the dielectric is scaled down below 10 nm. These can refer to articles "Flash Technology: Challenge and Opportunities", Raghupathy V. Giridhar, Jap. J. Appl. Phys. Vol. 35 pp. 6347-6350 (1996) and K. Yoshikawa et al., "Comparison of Current Flash EEPROM Erasing Methods: Stability and How to Control", IEDM, Tech. Dig., p595 (1992).